1. Field of the Invention
The present invention relates generally to a semiconductor device, and more particularly, to a bonding pad structure of integrated circuits.
2. Description of the Prior Art
As known in the art, to form a chip package, an integrated circuit chip is attached to a chip carrier such as a leadframe or a package substrate in an assembly process. Wire bonding is then carried out after the integrated circuit chip is attached to the chip carrier. During a wire-bonding process, bond wires are attached one at a time to respective bonding pads or input/output (I/O) pads on the integrated circuit chip, and the other end of the bond wire may be attached to a lead, a bonding pad, or a finger on the chip carrier.
Typically, a wire-bonding process includes the following steps. Firstly, an initial ball is formed at a tip end of a wire passing through a capillary of a wire bonder and the initial ball is pressure-bonded onto the bonding pad of the chip. Thereafter, the capillary is moved upward to a predetermined height away from the pressure-bonded ball, and then the capillary is moved toward a bonding site on the chip carrier, thereby the wire electrically and mechanically connects the bonding pad of the chip and the chip carrier.
Low-k and/or ultra low-k dielectric materials have been widely used for the inter-metal dielectric (IMD) layers to reduce RC delay and parasitic capacitances. However, as the dielectric constant decreases, the strength of the dielectric material decreases. Hence, many low-k dielectric materials are highly susceptible to cracking or lack the strength needed to withstand the stress exerted on the pad during wire bonding. For example, pad lifting phenomenon has been observed during wire-bonding process due to bonding pad delamination and insufficient dielectric strength under the bonding pad.
Thus, a need exists for an improved bonding pad structure that can sustain the stress exerted on it by a wire bonding process, which is capable of solving the prior art pad lifting problem.